This invention relates generally design automation of Very Large Integrated Circuits (VLSI), and more particularly to waveform modeling and propagation in statistical static timing analysis of digital circuits.
Static timing analysis (STA) has been used to verify the timing correctness of VLSI circuits. In particular, STA analyzes the VLSI circuits to determine the earliest and latest possible signal arrival times on each logic path or node by propagating signals throughout the gates and interconnects that form the path. The accuracy of timing analysis is heavily dependent on the modeling and propagation of digital signals throughout a design timing graph. The most common and widely used model for transition waveforms of digital signals is the well-known saturated ramp model. The use of the saturated ramp model eases the timing analysis since each voltage waveform is uniquely defined by its arrival time and transition time, also referred to as slew.
However, in a real design, the digital signal's shape could be very different from that of the saturated ramp. The actual shape of the gate or interconnect output signals depends on many factors including: the input signal waveform applied to the gate or interconnect, the gate and interconnect topology, the nonlinearities of the gate input capacitances, the coupling and power supply noise, etc.
It has been shown that the saturated ramp model is not sufficiently accurate for modeling the complex behavior of signals in high speed deep submicron VLSI circuits. Approximating signal waveforms by saturated ramps can incur as much as 19% error in final timing results. To overcome this problem, there have been several attempts to represent signal waveforms with more advanced models; such as piecewise linear waveforms, Weibull, Gamma and even arbitrary functions. These proposed models have helped to reduce the error of calculating arrival times by as much as 50-80%. These modeling techniques are advantageous, in particular, for static timing with a current source driver model or transistor level timing (TLT) analysis. Both the current source driver model and TLT analysis can easily handle complex waveforms and provide higher accuracy when operating with advanced waveform models. These models have also been employed for accurate coupling noise analysis as well as signal propagation through interconnects.
As complementary metal-oxide-semiconductor (CMOS) technology moves toward ultra deep sub-micron (UDSM) technologies, variability becomes the major obstacle for designing high-performance VLSI circuits. Therefore, there is a need for an advanced analysis tool which is capable of handling variability that stems from imperfect CMOS manufacturing processes, environmental factors, and device fatigue phenomena. Variability makes it difficult to verify that a chip will function correctly before releasing it for manufacturing.
Statistical static timing analysis (SSTA) is one approach that addresses issues associated with variability. As with its STA counterpart, today's SSTA tools only propagate two components of the digital signals (i.e., arrival time and transition time) by interpreting them as random variables or, perhaps, functions of process parameters modeled as random variables. Despite improving the accuracy of STA, advanced models of signal waveforms are still not very popular for SSTA since SSTA requires variational waveform modeling. The variational waveform modeling can be easily constructed for saturated ramp models of signal waveforms by representing signal transition times and arrival times as random quantities. However, the extension to the advanced models is not straightforward. For instance, one can model the signals with an exponential function and evaluate the timing constant of the exponent as a random quantity. This timing constant is proportional to the slew of a saturated ramp signal. However, an exponential waveform model has only marginal accuracy benefits compared to a traditional saturated ramp model and is not appropriate to mimic the accuracy of more advanced waveform models.
Modeling arbitrary signal waveforms with random functions due to the effect of environmental and process variations has also been studied for use in SSTA. In particular, it has been proposed to consider the crossing time of each point of the signal transition as a random quantity. To do that, the signal waveforms are modeled with Marcovian random processes. However, the definition of Marcovian random processes is too broad and contains a wide range of random functions. One of the main features of a Marcovian process is the dependence of each point only on its immediate history. This dependency is statistical, which means that probabilities of the new state depend on the previous states. Waveforms in manufactured chips belong to much narrower class of random functions. Their main property is the fact that the waveform shape can be fully determined by the actual values of environmental and process parameters. In addition, proposed point-wise variational waveform modeling is not efficient for SSTA since each signal is represented with rather a large number of random quantities in canonical, or first order linear, forms. This type of variational waveform modeling results in high memory consumption and it is highly inefficient for production use.
Therefore, there is a need for a modeling technique for waveform variation that can be used for SSTA.